1. Field of the Invention
The present invention relates generally to a control circuit for data transfer between a main memory and a register file in a digital data processing system, and more specifically to such a control circuit which is capable of markedly reducing execution time of the data transfer and by which a microprogram dedicated to the data transfer is no longer required.
2. Description of Related Art
As is known in the art, a register file is a hardware storage area for temporarily storing data applied from a main memory. The data stored in the register file can be again transferred to the main memory as requested. The register file includes a plurality of registers each of which is capable of storing one word.
In order to specify a plurality of registers (or a single register) for data transfer between the main memory and the register file, a so-called save area mask (SAM) data is applied to a control circuit which is operatively coupled to the register file. The SAM data is used to generate a register file address(es).
Before turning to the present invention it is deemed preferable to discuss, with reference to FIGS. 1 and 2, a known technique for the above-mentioned data transfer.
FIG. 1 is a chart showing one example of the SAM data whose bit length is 16 in this particular case, and further illustrates a plurality of one-bit leftward shifts of the SAM data by a shift register (not shown) for determining the register file addresses. On the other hand, FIG. 2 schematically illustrates an example of a register file which, in this case, includes 16 registers each having 4-byte storage capacity.
It is assumed that the SAM data shown in FIG. 1 includes logic 1s at the 14th and 15th bit positions which indicate respectively the 14th and 15th registers of the register file (FIG. 2).
In order to generate register file addresses, a counter (not shown) should be provided to determine the number of one-bit left shifts of the SAM data until each of logic 1s is located at the leftmost bit position. In the illustrated case, a logic 1 at the 14th bit position is shifted to the leftmost bit position after 14 leftward shifts. Thus, a file register address generator (not shown) is able to determine the register address for the 14th register of the register file. Subsequently, a logic 1 at the 15th bit position of the SAM data is shifted to the leftmost bit position. Accordingly, the counter determines the register file for the 15th register of the register file.
However, the aforesaid known technique has encountered the problem in that a large number of one-bit shifts of the SAM data are inevitably required for determining the register file addresses. Thus, the data transfer according to the known technique is considerably slow in time. In the worst case, one-bit shifts of the almost full length of the SAM data is undesirably required as discussed above. Accordingly, it is highly desirable to effectively accelerate the data transfer.
Further, the known technique has encountered another problem in that it requires a microprogram which is dedicated to the generation of the register file addresses.